# add VI1 in post std_filler stage to avoide VI1 drc violations.
#setViaGenMode -respect_stdcell_geometry true -use_trim_metal_enclosure true -optimize_cross_via true -partial_overlap_threshold 0 -ignore_DRC false
#editPowerVia -bottom_layer ME1 -top_layer ME2 -add_vias 1 -orthogonal_only 0
#setViaGenMode -reset

